1. Field of the Invention
This invention relates to high power Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFET) and more particularly to high power MOSFET's having planar construction and high current handling capability per unit of chip area.
2. Description of the Prior Art
The trend in electrical power systems, especially in space, military and aviation systems, is towards higher frequency, voltage, and current. Recently, power semiconductor devices have been developed in MOS configurations. It appears that MOS devices can be designed to handle higher power in switching applications than either the bipolar or junction-field-effect-transistor (JFET) devices typically used in such applications. The attractive features of MOS devices include: no charge storage, therefore no delay time at turn-off; a positive temperature coefficient of resistance, therefore they can easily be operated in parallel; no secondary breakdown; and a high input impedance. The advantage of power MOS devices over JFET devices is that more channel width can be designed into a unit of chip area and more charge can be controlled per unit of channel area.
Sigg et al described a double-diffused device (D-MOS) in an article entitled "D-MOS Transistor for Microwave Applications" published in IEEE Transactions on Electron Devices, ED-19, 45-53 (1972). The D-MOS is of planar construction and a top surface contact is made to the drain. The design permits the device to support a high drain voltage and yet have a short channel length thereby providing a high transconductance. The gate oxide need not support the drain-to-source voltage, thereby allowing a much thinner gate oxide to be used and permitting control of the device with lower gate voltages. This further increases the transconductance.
Kooi and Ragle in an article, "MOS Moves Into Higher Power Applications", Electronics, June 24, 1976, described an anisotropically etched V groove (VMOS) and built short channel MOS transistors into the walls of the V groove. This design has the advantage that the drain contact is made on the bottom of the silicon slice and therefore a large amount of channel width can be packed into a given chip area increasing the transconductance. This design also has the desirable feature that the high drain voltage is supported away from the gate oxide.
Both of the above devices have the unattractive feature of high input capacitance because the gate metal overlaps the source. The V groove device has the disadvantage that the anisotropically etched V groove exposes the &lt;111&gt; planes with their characteristically high fixed charge density and low carrier mobility.
Oakes et al described a transistor built into U-shaped grooves in the silicon in an article entitled "A Power Silicon Microwave MOS Transistor" published in IEEE Transactions On Microwave Theory and Techniques, MTT-24, 306-311 (1976). This design possesses the advantages of the DMOS and the VMOS designs and has two additional advantages. A gate metal deposition technique is used that closely aligns the gate metal over the channel thereby providing a lower input capacitance. Because the anisotropic etch is not used, the device exhibits higher carrier mobility than does the V groove device. It is a good device for microwave frequency applications but would not be suitable for high power at low frequencies.
Yoshida et al described a high power MOS device in an article entitled "A High Power MOSFET With A Vertical Drain Electrode And Meshed Gate Structure", IEEE J. Solid State Circuits, SC-11, 472-477 (August 1976). The device can handle 200 watts (20 A, 100 V) and can be operated at 180.degree. C. The device has two disadvantages, however. It is a p-channel device and thus does not take advantage of the higher mobility of electrons, and it has a very high input capacitance (2,000 pF).